module ikf_unsymmetrical
(
clk,
idata,
odata
);
input clk;
input wire [17:0] idata;
output wire [17:0] odata;
reg signed [3:0] filt_koef[8:0]; //коэф-ы фильтра
reg signed[17:0] RS[8:0]; //регистр сдвига
reg signed [17:0] filter;
reg signed [17:0] mult0, mult1, mult2, mult3, mult4, mult5, mult6, mult7, mult8;
reg signed[17:0] sumreg1, sumreg2, sumreg3, sumreg4, sumreg5, sumreg6, sumreg7, sumreg8;
wire signed [17:0] sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7;
integer i,j;
integer sum;
//----------инициализация массива---------//
initial
begin
filt_koef[0]=1'd1;
filt_koef[1]=2'd2;
filt_koef[2]=2'd3;
filt_koef[3]=-4'd4;
filt_koef[4]=3'd5;
filt_koef[5]=-4'd4;
filt_koef[6]=2'd3;
filt_koef[7]=2'd2;
filt_koef[8]=1'd1;
end
//----------------shift-----------------//
always@(posedge clk)
begin
RS[0]<=idata;
for(i=0;i<8;i=i+1)
RS[i+1]<=RS[i];
end
//=======================================//
//always@(posedge clk)
// begin
// for(j=0;j<9;j=j+1)
// begin
// sum = sum + RS[j]*filt_koef[j];
// end
// filter<=sum;
// sum=0;
//
// end
//
//assign odata = filter;
always @ (posedge clk)
begin
sumreg1 <= sum0;
sumreg2 <= sum1;
sumreg3 <= sum2;
sumreg4 <= sum3;
sumreg5 <= sum4;
sumreg6 <= sum5;
sumreg7 <= sum6;
sumreg8 <= sum7;
end
always@(posedge clk)
begin
mult0<=RS[0]*filt_koef[0];
mult1<=RS[1]*filt_koef[1];
mult2<=RS[2]*filt_koef[2];
mult3<=RS[3]*filt_koef[3];
mult4<=RS[4]*filt_koef[4];
mult5<=RS[5]*filt_koef[5];
mult6<=RS[6]*filt_koef[6];
mult7<=RS[7]*filt_koef[7];
mult8<=RS[8]*filt_koef[8];
end
assign sum0 = mult0 + mult1;
assign sum1 = mult2 + mult3;
assign sum2 = mult4 + mult5;
assign sum3 = mult6 + mult7;
assign sum4 = sumreg1 + sumreg2;
assign sum5 = sumreg3 + sumreg4;
assign sum6 = sumreg5 + sumreg6;
assign sum7 = sumreg7 + mult8;
assign odata = sumreg8;
endmodule
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