use ieee.std_logic_1164.all;
ENTITY and IS
PORT (
A, B : IN STD_LOGIC;
C : OUT STD_LOGIC);
END and;
ARCHITECTURE and_behaviour OF and IS
COMPONENT andgate
PORT(a, b : IN BIT; c : OUT BIT);
END andgate;
BEGIN
U1 : andgate(A => a, B => b, C => c);
END and_behaviour;
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