VHDL - Xilinx board - Seven segment display + buttons + LEDs + UART throw RS232 code (Clock Divisor only)

---------------------------------------------------------------------------------- -- Company: MordorBet -- Engineer: Urko Pineda -- -- Description: Divisor de CLK para botones, LEDs, UART, SSD, etc. -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity Divisor is Port( clk: in std_logic; rst: in std_logic; mode: in std_logic_vector(1 downto 0); div_clk: out std_logic ); end Divisor; architecture Behavioral of Divisor is signal div_clk_sig: std_logic; signal prescaler : unsigned (23 downto 0); begin divsys: process (clk, mode) begin if (rst = '1') then prescaler <= (others => '0'); elsif (rising_edge(clk)) then if (mode = "00") then if prescaler = X"C20" then prescaler <= (others => '0'); div_clk_sig <= not div_clk_sig; else prescaler <= prescaler + "1"; end if; elsif (mode = "01") then if prescaler = X"4ABC20" then prescaler <= (others => '0'); div_clk_sig <= not div_clk_sig; else prescaler <= prescaler + "1"; end if; elsif (mode = "11") then if prescaler = X"4ABC20" then prescaler <= (others => '0'); div_clk_sig <= not div_clk_sig; else prescaler <= prescaler + "1"; end if; elsif (mode = "10") then if prescaler = X"4ABC20" then prescaler <= (others => '0'); div_clk_sig <= not div_clk_sig; else prescaler <= prescaler + "1"; end if; else div_clk_sig <= clk; end if; end if; end process; div_clk <= div_clk_sig; end Behavioral;