VHDL - Xilinx board - Seven segment display + buttons + LEDs + UART throw RS232 code (Sync baudrate only)

---------------------------------------------------------------------------------- -- Company: MordorBet -- Engineer: Urko Pineda -- -- Description: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.std_logic_ARITH.ALL; use IEEE.std_logic_UNSIGNED.ALL; entity BR_GENERATOR is generic (DIVIDER_WIDTH: integer := 12); Port ( clk : in std_logic; RX_ENABLE : in std_logic; CLK_TXD : out std_logic; TX_ENABLE : in std_logic; CLK_SERIAL : out std_logic ); end BR_GENERATOR; architecture PRINCIPAL of BR_GENERATOR is -- Change the following constant to your desired baud rate -- One Hz equal to one bit per second signal COUNT_BRG : STD_LOGIC_VECTOR(DIVIDER_WIDTH-1 downto 0):=(others=>'0'); signal COUNT_BRG_TXD : STD_LOGIC_VECTOR(DIVIDER_WIDTH-1 downto 0):=(others=>'0'); constant BRDVD : std_logic_vector(DIVIDER_WIDTH-1 downto 0) := X"516"; -- 50MHz - 38400 baud begin TXD : process (clk) begin if (clk='1' and clk'event) then if (COUNT_BRG_TXD=BRDVD) then CLK_TXD<='1'; COUNT_BRG_TXD <= (others=>'0'); elsif (TX_ENABLE='1') then CLK_TXD<='0'; COUNT_BRG_TXD <= COUNT_BRG_TXD + 1; else CLK_TXD<='0'; COUNT_BRG_TXD <= (others=>'0'); end if; end if; end process TXD; RXD : process (clk) begin if (clk='1' and clk'event) then if (COUNT_BRG=BRDVD) then COUNT_BRG <= (others=>'0'); CLK_SERIAL<='1'; elsif (RX_ENABLE='1') then COUNT_BRG<=COUNT_BRG+1; CLK_SERIAL<='0'; else CLK_SERIAL<='0'; COUNT_BRG<= '0' & BRDVD(DIVIDER_WIDTH-1 DOWNTO 1); end if; end if; end process RXD; end PRINCIPAL;